This invention relates to integrated circuit device fabrication methods and, more particularly, to methods of forming field oxide isolation regions in semiconductor substrates.
Improved active device isolation techniques are desired in order to facilitate ongoing attempts to increase integration density in integrated circuit devices by designing devices having reduced unit cell size. Conventional device isolation techniques include local oxidation of silicon (LOCOS) and shallow trench isolation (STI) techniques, for example. Such device isolation techniques are disclosed in U.S. Pat. Nos. 5,677,234, 5,750,433, 5,753,562, 5,837,595, 5,858,842 and 5,885,883.
But, such techniques as LOCOS may not be appropriate for state-of-the-art high integration devices because they typically result in the formation of isolation regions having bird""s beak oxide extensions which typically consume relatively large amounts of surface area. To address this and other problems, STI techniques have been developed. One such technique is illustrated by FIGS. 30A-30E. In particular, FIG. 30A illustrates the steps of forming a pad oxide layer 3, a pad nitride layer 4, a high temperature oxide (HTO) layer 5 and an anti-reflective layer 6 on a semiconductor substrate 2. A photoresist layer 10 is then patterned on the anti-reflective layer 6. A trench mask 8 is then formed by performing an etching step using the patterned photoresist layer 10 as an etching mask. As illustrated by FIG. 30B, another etching step is then performed to define a trench 12 in the substrate 2, using the trench mask 8 as a etching mask. During the etching step, the an anti-reflective layer 6 may also be removed.
Referring now to FIG. 30C, a thermal oxide layer 14 is then formed in the trench to remove etching damage. A trench isolation layer comprising an undoped silicate glass (USG) layer 15 and a PE-TEOS oxide layer 16 (for reducing stress in the USG layer), is then formed to fill the trench 12. As illustrated by FIG. 30D, a planarization step (e.g., CMP) is then performed, using the pad nitride layer 4 as an etch stop layer. Then, as illustrated by FIG. 30E, the pad nitride layer 4 and pad oxide layer 3 are sequentially removed to define a trench isolation region 18.
Unfortunately, because the substrate 2 may have a substantially different coefficient of thermal expansion than the USG layer 15 in the trench 12, substantial stresses may develop in the substrate 2 during back-end processing. These stresses may adversely influence the device characteristics of active devices formed in active regions extending adjacent the trench isolation region 18. The subsequent formation of an oxide layer on the active regions (e.g., gate oxide layers) may also act to increase the degree of stress in the substrate 2, due to volume expansion in the trench isolation region 18. Grain dislocation defects and pits may also be generated at the bottom corners and sidewalls of the trench in response to the volume expansion. Such defects may lead to increases in junction leakage currents in adjacent active devices, and decreases in reliability and yield.
To inhibit the formation of grain dislocations and pits at the corners and sidewalls of the trench isolation regions during back end processing steps, silicon nitride layers have been used in trench isolation regions to provide stress relief. Such silicon nitride stress relief layers are described in U.S. Pat. No. 5,447,884 to Fahey et al., entitled xe2x80x9cShallow Trench Isolation With Thin Nitride Linerxe2x80x9d. FIG. 1 is also a graph that illustrates the reduction in junction leakage currents that may occur when silicon nitride stress relief layers (SiN) are provided in trench isolation regions. Here, the leakage currents were measured as the drain xe2x80x9coffxe2x80x9d currents for MOSFETs formed adjacent a trench isolation region. These currents were measured by grounding the gate electrode, the source region and the substrate and applying a voltage of 3.3 volts to the drain region of the MOSFET. In FIG. 1, the symbols -xe2x96xa1- designate the leakage currents when silicon nitride stress relief layers are not used and the symbols -∘- designate the leakage currents when silicon nitride stress relief layers are provided.
Referring now to FIGS. 24, a conventional method of forming a trench isolation region having a silicon nitride stress-relief layer therein will be described. In particular, FIG. 2 illustrates the steps of forming a pad oxide layer 53 on a surface of a semiconductor substrate 51 and then forming a silicon nitride masking layer 55 on the pad oxide layer. A conventional etching step is then performed to etch a trench in the substrate 51, using the masking layer 55 as an etching mask. The sidewalls and bottom of the trench are then thermally oxidized to define a sidewall insulating layer 56. A blanket silicon nitride stress-relief layer 57 is then deposited onto the sidewall insulating layer 56 and onto a sidewall and upper surface of the masking layer 55. A relatively thick blanket trench isolation layer 59 is then deposited onto the stress-relief layer 57. The trench isolation layer 59 may comprise silicon dioxide and may be formed by a chemical vapor deposition (CVD) technique. A planarization step is then performed to etch back the trench isolation layer 59 and the stress-relief layer 57, using the masking layer 55 as a planarization stop layer. This planarization step may be performed by chemically-mechanically polishing (CMP) the trench isolation layer 59 and the stress-relief layer 57 until the masking layer 55 is exposed.
Referring now to FIG. 3, an isotropic wet etching step is then performed to selectively and preferably completely remove the masking layer 55 and expose the pad oxide layer 53. This etching step may be performed using an etchant that selectively etches silicon nitride at much higher rates than silicon dioxide (e.g., phosphoric acid H3PO4). However, during this etching step, the silicon nitride stress-relief layer 57 may also be etched in the vertical direction xe2x80x9cVxe2x80x9d and in the lateral direction xe2x80x9cLxe2x80x9d as the silicon nitride masking layer 55 is consumed. As illustrated, this vertical and lateral etching may cause the stress-relief layer 57 to become recessed to a level below the surface of the substrate 51. As will be understood by those skilled in the art, these recesses (or xe2x80x9cdentsxe2x80x9d) may adversely effect the isolation characteristics of the resulting trench isolation region if steps are not taken to fill the recesses with additional stress-relief material during subsequent processing steps. For example, the presence of the recesses may negatively impact the refresh characteristics of devices such as dynamic random access memory (DRAM) devices and may increase an inverse narrow width effect (INWE) in field effect transistors. Increases in INWE may also increase threshold voltage levels and cause a parasitic hump phenomenon to develop in the transistor""s I-V characteristics. The presence of the recesses may also increase the likelihood that conductive bridges will be formed between adjacent active regions if the recesses become filled with electrically conductive material during subsequent process steps. In particular, if the degree of recession is significant enough, the recesses illustrated by region A in FIG. 4 may remain even after a selective etching step is performed to etch-back the pad oxide layer 53 and the trench isolation layer 59 and define a final trench isolation region having a planarized trench isolation layer 59xe2x80x2 and silicon nitride stress-relief layer 57xe2x80x2.
Thus, notwithstanding the above described methods, there continues to be a need for improved methods of forming trench isolation regions and trench isolation regions formed thereby.
It is therefore an object of the present invention to provide improved methods of forming trench isolation regions and trench isolation regions formed thereby.
It is another object of the present invention to provide methods of forming trench isolation regions having reduced susceptibility to void defects therein and trench isolation regions formed thereby.
It is still another object of the present invention to provide methods of forming trench isolation regions having low stress characteristics and trench isolation regions formed thereby.
These and other objects, advantages and features of the present invention may be provided by methods of forming trench isolation regions that include the steps of forming a semiconductor substrate having a trench therein and a masking layer thereon extending adjacent the trench. The masking layer may comprise silicon nitride. A recess-inhibiting layer is then formed on a sidewall of the trench and on a sidewall of the masking layer. Next, a stress-relief layer is formed on the recess-inhibiting layer. This stress-relief layer extends opposite the sidewall of the trench and opposite the sidewall of the masking layer and may comprise silicon nitride. The trench is then filled with a trench isolation layer. A sequence of planarization or etch-back steps are then performed to remove the masking layer and also align an upper surface of the trench isolation layer with a surface of the substrate. In particular, at least a portion of the masking layer is removed using a first etchant (e.g., phosphoric acid) that selectively etches the masking layer and the stress-relief layer at faster rates than the first recess-inhibiting layer. According to a preferred aspect of the present invention, the recess-inhibiting layer is formed directly on a sidewall of the masking layer in order to limit the extent to which the outer surfaces of the stress-relief layer are exposed to the first etchant. In this manner, recession of the stress-relief layer and the voids that may subsequently develop as a result of the recession can be reduced. According to another preferred aspect of the present invention, multiple thin stress-relief layers are provided. These multiple stress-relief layers can provide a degree of stress-relief that is comparable with a single much thicker stress-relief layer. Moreover, the use of thin stress-relief layers can reduce the degree of recession that may occur with each layer by reducing the surface area of each stress-relief layer that is exposed to the first etchant when the masking layer is being removed.
According to another embodiment of the present invention, methods of forming trench isolation regions include the steps of forming a semiconductor substrate having a trench therein and a silicon nitride masking layer thereon surrounding the trench and then forming a silicon layer on the sidewall of the trench and on a sidewall and upper surface of the masking layer. The silicon layer, which may comprise polysilicon or amorphous silicon (a-Si), is then converted into a silicon dioxide recess-inhibiting layer using a thermal oxidation technique. A silicon nitride stress-relief layer is then formed on the recess-inhibiting layer. This step is then followed by the steps of forming a trench isolation layer on the stress-relief layer and removing the masking layer using a first etchant that selectively etches the masking layer and the stress-relief layer at faster rates than the recess-inhibiting layer. The trench isolation layer is then etched using a second etchant that selectively etches the trench isolation layer and the recess-inhibiting layer at faster rates than the stress-relief layer. Thus, according to this embodiment of the present invention, a preferred recess-inhibiting layer may be formed as a silicon dioxide layer by first depositing a silicon layer on a sidewall of the masking layer and then thermally oxidizing the silicon layer.
According to still a further embodiment of the present invention, trench isolation regions are provided having a plurality of thin silicon nitride stress-relief layers therein. Taken together, these plurality of stress-relief layers can provide a high degree of stress relief. Moreover, because each stress-relief layer is formed as a thin layer, the likelihood of substantial recession in response to chemical etching steps is reduced. In particular, trench isolation regions according to the present invention include a semiconductor substrate having a trench therein and an electrically insulating trench isolation layer in the trench. In addition, a plurality of silicon nitride stress-relief layers and a plurality of silicon dioxide recess-inhibiting layers are disposed in alternating sequence between the trench isolation layer and a sidewall of the trench. The plurality of silicon nitride stress-relief layers may have respective thicknesses of less than about 200 xc3x85.